Multi-level package for a memory module
US6737738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Jul 16, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A high density, low profile, three dimensional memory module having multi-level semiconductor packages mounted on one or opposite sides of a printed wiring board. Each multi-level package of the memory module contains an upper level DRAM integrated circuit package that is surface mounted on the printed wiring board and at least one lower level DRAM integrated circuit package that is surface mounted on the printed wiring board below the upper level package, such that the upper and lower level packages are stacked one above the other. The upper level package is preferably a thin small outline package, and the lower level package is preferably a leadless chip scale package. The leads of the upper level package are of sufficient length so that the standoff height of the upper level package establishes a clearance thereunder in which to receive the lower level package. The lower level package is characterized by a smaller footprint and profile than the corresponding footprint and profile of the upper level package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.