Circuit configuration for detecting the current in a load transistor
US6737856B2 · kind B2 · utility
11Cited by
13References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2001 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Nov 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0027
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention relates to a circuit arrangement having a load transistor (T1) and a current sensing transistor (T2) coupled to the load transistor (T1), wherein a switch arrangement (S) having at least one first switch (S1; S1a, S1b) is connected downstream of the current sensing transistor (T2) in order to connect the current sensing transistor (T2) to a first or second evaluation circuit (BL1, BL2) depending on a control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.