EEPROM memory comprising means for simultaneous reading of special bits of a first and second type
US6738286B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Oct 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable and programmable memory (EEPROM) includes a memory array containing memory cells connected to word lines arranged in rows and to bit lines arranged in columns. The memory array includes a first special zone for storing special bits of a first type, and a second special zone for storing special bits of a second type. The first special zone includes a first row of memory cells connected to a first word line, wherein N1 memory cells are connected to N1 bit lines of a determined column of the memory array. The second special zone includes a second row of memory cells connected to a second word line, wherein N2 memory cells are connected to N2 other bit lines of the determined column. The N1 bit lines are not connected to the second row of memory cells, and the N2 bit lines are not connected to the first row of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.