Dynamic memory device and method for controlling such a device

US6738304B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Alexander Benedix · Hersbruck, DE
• Stefan Dankowski · Hersbruck, DE
• Reinhard Dueregger · Poing, DE
• Wolfgang Ruf · Friedberg, DE

Key dates

• Filing date: Oct 30, 2002
• Grant date: May 18, 2004
• Expiry date: Oct 30, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/406
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

According to one embodiment, a dynamic memory is provided. The dynamic memory can include a memory matrix having a plurality of memory cells arranged in rows and columns. The memory cells in a row can be connected by in each case one of a plurality of word lines. The memory cells in a column can be connected by in each case one of a plurality of bit lines. The dynamic memory can also include a sense amplifier for reading data from the memory cells via the plurality of bit lines. Further, the dynamic memory can include a row address decoder and a column address decoder for generating memory-internal address in a manner dependent on a memory-external address signal. The dynamic memory can also include a sequence control device for cyclically generating refresh addresses for carrying for carrying out a refresh operation of the memory cells.