Use of enable bits to control execution of selected instructions
US6738892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1999 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Oct 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information control pipeline (13) parallels the processor's instruction pipeline (3), contains digital control information in respect of the instruction placed in the instruction pipeline and accompanies that instruction until all component operations prescribed within the instruction have been executed. When at the end of the pipeline, the instruction is presented for execution to a respective functional execution unit (7) of the processor, the respective functional execution unit accesses and uses the control information as a condition to instruction execution. Depending upon the processor, the control information may contain one or more bits, referred to as enable bits, as may be set enabled, indicating that an associated operation in the instruction is to be executed, or by software set disabled, indicating that the associated operation is masked, such as by an exception handler (9) when returning from a resolved exception.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.