Low latency synchronization of asynchronous data
US6738917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2001 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Oct 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low latency method of synchronizing asynchronous data to a core clock in a receiving device. A communication referenced to a transmitting clock that is asynchronous to the core clock is received at a receiving device. The communication includes a synchronization signal which is propagated through a synchronizer in the receiving device to synchronize the signal to the core clock. Upon receipt of the synchronization signal by the synchronizer, a load pointer for loading received data into a buffer synchronous with the transmitting clock is reset. Upon completion of the propagation of the synchronization signal through the synchronizer, an unload pointer for unloaded the data from the buffer synchronous with the core clock is reset. The unload pointer is then offset by an amount that compensates for the delay incurred while the synchronization propagated through the synchronizer. Thereafter, the position of the unload pointer is dynamically adjusted based on the accumulated amount of data loaded into the buffer and the accumulated amount of data unloaded from the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.