Method for prediction random defect yields of integrated circuits with accuracy and computation time controls

US6738954B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Archibald J. Allen · Shelburne, US
• Wilm E. Donath · New York, US
• Alan Dziedzic · Newburgh, US
• Mark A. Lavin · Katonah, US
• Daniel N. Maynard · Craftsbury Common, US
• Dennis M. Newns · Yorktown Heights, US
• Gustavo E. Tellez · South Burlington, US

Key dates

• Filing date: Aug 10, 2000
• Grant date: May 18, 2004
• Expiry date: Jun 5, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31705
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error lim…