Semiconductor memory cell and method of forming same
US6740921B2 · kind B2 · utility
64Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Dec 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.