Semiconductor memory devices having dummy active regions
US6740940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.