Distributed translation look-aside buffers for graphics address remapping table
US6741258B1 · kind B1 · utility
33Cited by
7References
15Claims
0Family size
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Key dates
| Filing date | Jan 4, 2000 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Jan 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a main memory device which stores information for translating a virtual address into a physical address in response to one of a plurality of processing devices. A memory control/interface device is coupled to the main memory device. The memory control/interface device, which may access the information stored in the main memory device, has a separate translation look-aside buffer for each processing device. Each translation look-aside buffer can buffer the information for use in translating in response to the respective processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.