Method of making a wafer level chip scale package
US6743660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jun 9, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49222
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.