Floating gate memory fabrication methods comprising a field dielectric etch with a horizontal etch component
US6743675B2 · kind B2 · utility
32Cited by
13References
21Claims
0Family size
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Inventor
Key dates
| Filing date | Oct 1, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Oct 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon nitride layer (120) is formed over a semiconductor substrate (104) and patterned to define isolation trenches (130). The trenches are filled with dielectric (210). The nitride layer is removed to expose sidewalls of the trench dielectric (210). The dielectric is etched to recess the sidewalls away from the active areas (132). Then a conductive layer (410) is deposited to form floating gates for nonvolatile memory cells. The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.