Method of manufacturing a semiconductor device
US6743682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Apr 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer. A conductive layer 30 is applied filling the recess 19 and the contact window 28,29, which conductive layer 30 is subsequently shaped into the gate structure 21 and a contact structure 26,27 establishing an electrical contact with the surface 2 of the semiconductor body 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.