Multichip semiconductor package device
US6744126B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | May 7, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S439/912
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip semiconductor package device includes first and second devices and a conductive bond. The first device includes an insulative housing, a first semiconductor chip and a conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The conductive trace includes a terminal that extends through the central portion and a lead that protrudes laterally from and extends through the side surface. The second device includes a second semiconductor chip, extends into the cavity and is positioned within and does not extend outside a periphery of the cavity. The conductive bond is inside the cavity, on the terminal and contacts and electrically connects the first and second devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.