Semiconductor chip, memory module and method for testing the semiconductor chip
US6744127B2 · kind B2 · utility
8Cited by
8References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | May 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lowermost layer of control chips carries on it layers of memory chips. The memory chips are contacted via looped-through contacts that reach from one side of the other side of the memory chips and they are driven by the control chips that contain the test circuit for the memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.