Stacked chip-size package type semiconductor device capable of being decreased in size
US6744141B2 · kind B2 · utility
23Cited by
10References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device including a substrate, a first semiconductor chip directly or indirectly on the substrate, and a second semiconductor chip located on the first semiconductor chip, the second semiconductor chip has a larger dimension than that of the first semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.