Latching dynamic logic structure, and integrated circuit including same
US6744282B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2003 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Mar 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latching dynamic logic structure is disclosed including a static logic interface, a dynamic logic gate, and a static latch. The static logic interface receives a data signal, a select signal, and a clock signal, and produces a first intermediate signal such that when the select signal is active, the first intermediate signal is dependent upon the data signal for a period of time following a clock signal transition. The dynamic logic gate discharges a dynamic node following the clock signal transition dependent upon the first intermediate signal. The static latch produces an output signal assuming one of two logic levels following the clock signal transition, and assuming the other logic level in the event the dynamic node is discharged. A scan-testing-enabled version of the latching dynamic logic structure is described, as is an integrated circuit including the latching dynamic logic structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.