System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise
US6744301B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2000 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Nov 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.