Source-biased memory cell array
US6744659B1 · kind B1 · utility
12Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Dec 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array employs “source-biasing”, wherein a bias voltage is applied to the sources of one or more FETs within a memory cell to reduce their “off” state sub-threshold leakage currents. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs, and ground for FETs which are being read. A plurality of source-bias circuits provides the selectively switched bias voltages to the memory cells in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.