DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
US6744676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2003 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Feb 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.