Capacitive multidrop bus compensation
US6745268B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2000 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jul 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.