Terry R. Lee
141Patents
32h-index
47Co-inventors
90Inventor score
Filing activity: Mar 18, 1985 → Aug 19, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5935263A | Method and apparatus for memory array compressed data testing | Physics | 472 | Expired |
| US6442644B1 | Memory system having synchronous-link DRAM (SLDRAM) devices and controller | Emerging Cross-Sectional Technologies | 382 | Expired |
| US8106520B2 | Signal delivery in stacked device | Emerging Cross-Sectional Technologies | 285 | Active |
| US6356106B1 | Active termination in a multidrop memory system | Electricity | 226 | Expired |
| US7120727B2 | Reconfigurable memory module and method | Physics | 186 | Expired |
| US6820181B2 | Method and system for controlling memory accesses to memory modules having a memory hub architecture | Physics | 148 | Expired |
| US6662304B2 | Method and apparatus for bit-to-bit timing correction of a high speed memory bus | Physics | 137 | Expired |
| US6284571A | Lead frame assemblies with voltage reference plane and IC packages including same | Electricity | 129 | Expired |
| US6871253B2 | Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection | Emerging Cross-Sectional Technologies | 110 | Expired |
| US5276642A | Method for performing a split read/write operation in a dynamic random access memory | Physics | 109 | Expired |
| US7428644B2 | System and method for selective memory module power management | Emerging Cross-Sectional Technologies | 105 | Expired |
| US6982892B2 | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules | Emerging Cross-Sectional Technologies | 100 | Expired |
| US6735709B1 | Method of timing calibration using slower data rate pattern | Electricity | 97 | Expired |
| US7437579B2 | System and method for selective memory module power management | Emerging Cross-Sectional Technologies | 90 | Expired |
| US6044429A | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths | Physics | 72 | Expired |
| US6548757B1 | Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies | Electricity | 64 | Expired |
| US5231605A | DRAM compressed data test mode with expected data | Physics | 59 | Expired |
| US6889357B1 | Timing calibration pattern for SLDRAM | Electricity | 58 | Expired |
| US5930182A | Adjustable delay circuit for setting the speed grade of a semiconductor device | Physics | 46 | Expired |
| US6330194A | High speed I/O calibration using an input path and simplified logic | Physics | 46 | Expired |
| US6898726B1 | Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations | Physics | 46 | Expired |
| US6549036B1 | Simple output buffer drive strength calibration | Electricity | 45 | Expired |
| US6392948B1 | Semiconductor device with self refresh test mode | Physics | 45 | Expired |
| US6256235A | Adjustable driver pre-equalization for memory subsystems | Physics | 43 | Expired |
| US6961259B2 | Apparatus and methods for optically-coupled memory systems | Physics | 42 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.