Multi-processor computer system with lock driven cache-flushing system
US6745294B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Apr 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.