Method of masking corrupt bits during signature analysis and circuit for use therewith
US6745359B2 · kind B2 · utility
30Cited by
7References
55Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of masking corrupt bits in test response pattern scan chains in an integrated circuit, comprising loading and applying a set of test patterns in the scan chains so as to obtain corresponding test response patterns; and masking bits of the test response patterns located in scan chains identified by a chain mask and at a position identified by a position mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.