Bus architecture for system on a chip
US6745369B1 · kind B1 · utility
52Cited by
16References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jan 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.