Method for selecting an optimal level of redundancy in the design of memories
US6745370B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jun 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect sizes, and the signatures of the electrical responses of faulted circuits to input test stimuli are determined. A statistical frequency distribution for both the signatures for a ratio of defect sizes on each of the process layers, and for the occurrences of selected combinations of the signatures are determined. A ratio of the signature distribution for different numbers of redundancy units, and the die area for each of the different numbers of redundancy units are determined. The number of usable die per wafer is determined from the signature distribution and the die area. A level of redundancy that maximizes the number of usable die per wafer is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.