Julie Segal
8Patents
6h-index
10Co-inventors
60Inventor score
Filing activity: Apr 2, 1997 → Jul 10, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6795953B2 | Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design | Physics | 192 | Expired |
| US6092030A | Timing delay generator and method including compensation for environmental variation | Physics | 17 | Expired |
| US6745370B1 | Method for selecting an optimal level of redundancy in the design of memories | Electricity | 17 | Expired |
| US6701477B1 | Method for identifying the cause of yield loss in integrated circuit manufacture | Physics | 14 | Expired |
| US6920596B2 | Method and apparatus for determining fault sources for device failures | Physics | 10 | Expired |
| US6810510B2 | Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout | Physics | 8 | Expired |
| US6780656B2 | Correction of overlay offset between inspection layers | Physics | 1 | Expired |
| US11295962B2 | Low temperature process for diode termination of fully depleted high resistivity silicon radiation detectors that can be used for shallow entrance windows and thinned sensors | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.