Method for forming a semiconductor device having high-K gate dielectric material
US6746900B1 · kind B1 · utility
9Cited by
10References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2003 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Feb 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.