Method of fabricating self-aligned cross-point memory array
US6746910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Sep 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a self-aligned cross-point memory array includes preparing a substrate, including forming any supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N+ region; implanting ions to form a shallow P+ region on the N+ region to form a P+/N junction; depositing a barrier metal layer on the P+ region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer or silicon nitride layer on the bottom electrode layer; patterning and etching the structure to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench; depositing oxide to fill the trench; patterning and etching the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layer, patterning and etching the top electrode layer, and completing the memory array structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.