Method of fabricating a vertical quadruple conduction channel insulated gate transistor
US6746923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Apr 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.