Inventor · Chambéry, FR

Emmanuel Josse

9Patents

2h-index

15Co-inventors

44Inventor score

Filing activity: Apr 2, 2002 → Oct 18, 2016

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6861684B2	Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor	Electricity	33	Expired
US6746923B2	Method of fabricating a vertical quadruple conduction channel insulated gate transistor	Electricity	16	Expired
US7504683B2	Integrated electronic circuit incorporating a capacitor	Electricity	2	Active
US9318372B2	Method of stressing a semiconductor layer	Electricity	1	Active
US9305828B2	Method of forming stressed SOI layer	Electricity	1	Active
US7078764B2	Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor	Electricity	1	Expired
US9876032B2	Method of manufacturing a device with MOS transistors	Electricity	0	Active
US9735772B2	Multi-orientation integrated cell, in particular input/output cell of an integrated circuit	Electricity	0	Active
US9543214B2	Method of forming stressed semiconductor layer	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.