MOS transistor in an integrated circuit and active area forming method
US6746935B2 · kind B2 · utility
3Cited by
14References
3Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 29, 2001 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Mar 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an active area surrounded with an insulating area in a semiconductor substrate, including the steps of forming in the substrate a trench surrounding an active area; filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area; forming a spacer at the periphery of said edge; and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.