Single poly EEPROM with reduced area

US6747308B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Jozef Mitros · Richardson, US
• Lily Springer · Dallas, US
• Roland Bucksch · Buch am Erlbach, DE

Key dates

• Filing date: Dec 30, 2002
• Grant date: Jun 8, 2004
• Expiry date: Dec 30, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2216/10

Abstract

An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.