Flip-chip packaging
US6747342B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Aug 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.