Programmable data device and method therefor
US6747477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Sep 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable data latch (21) is disclosed. The data latch comprises a master latch (34) operable to load data into the data latch (21) and a slave latch (36) operable to receive the data and produce the output (20) and inverted output of the data latch (21). Also provided is a plurality of programmable floating gate transistor (53, 54) wherein the “on” or “off” state of the floating gate transistor (53, 54) is determined by the data loaded into the data latch (21). A programming voltage supply (26) is supplied to the floating gate transistors (53, 54) which increases the threshold voltage of the floating gate transistor (53, 54) in the “on” state and produces a programmed transistor. The programmed transistor is operable to set the state of the data latch (21) upon subsequent use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.