Differential memory interface system
US6747483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Aug 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory interface system comprising a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit. The control interface is configured to drive a first and a second differential control output signal wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common voltage. The system also comprising a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, and the system also comprising the buffer unit coupled with the first power supply, the buffer unit configured to transfer data between the control interface and the memory interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.