Method and apparatus for multiple byte or page mode programming of a flash memory array
US6747899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.