Leakage control circuit
US6747904B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Dec 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A leakage control circuit and DRAM equipped therewith. The leakage control circuit includes a differential amplifier, a first voltage divider, a second voltage divider, MOS transistors, and a charge pump. The first voltage divider generates a first reference voltage. The second voltage divider generates a second reference voltage. The differential amplifier has a first input receiving the first reference voltage, a second input receiving the second reference voltage, and an output coupled to the input of the charge pump. MOS transistors have drains coupled to the first input of the differential amplifier, gates coupled to the output of the charge pump, and sources coupled to a ground potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.