Multiple non-contiguous block erase in flash memory
US6748482B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Feb 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory block erase operation permits multiple blocks to be erased simultaneously, even if the blocks are non-contiguous. A command sequence outputs multiple block addresses to the flash memory controller, which stores indicators of those addresses. When the command is completed, the flash memory initiates a block erase on all the specified blocks. The special command can be a multi-cycle bus command, made up of a sequence of single-cycle bus transfers using a standard format for the bus. The flash memory interface can contain the capability to interpret the command, retain the information transferred during the multiple bus cycles, and initiate the block erase operation after all the block addresses for that command have been received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.