Method and apparatus for utilizing renamed registers based upon a functional or defective operational status of the register
US6748519B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a mechanism for providing redundancy in the register file of a microprocessor such that registers having a defective operational status, as determined by testing, can be tolerated and the baseline specification of the microprocessor can be met. The present invention utilizes the register renaming capability of a microprocessor to allow additional registers, above those called for in the specification to be provided. The registers are then tested and those found “bad” are identified and avoided by the allocation/deallocation logic, which is used to assign registers to the various instructions being executed by the microprocessor. More particularly, the present invention maintains a list of physical registers in a register file that have a functional operational status and are available to be allocated to various instructions as they execute. The allocated registers are typically used to store interim data resulting from the execution of the assigned instruction. When the data in the rename register is complete it is then committed to the architecture by rewriting the results to an architected register. The present invention uses this rename capab…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.