Method and apparatus for testing path delays in a high-speed boundary scan implementation
US6748563B1 · kind B1 · utility
6Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Jul 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for testing path delays in a high-speed boundary scan implementation overcomes limitations imposed by pipelined high-speed clocking architectures used in integrated circuits. A special phase hold circuit provides a mechanism for clocking circuits undergoing dynamic tests, permitting the dynamic test to produce proper results when the integrated circuit under test is clocked with a high-speed distributed clock. The functional logic clock enable is pipelined to synchronize the functional mode clock with the test mode clock when the tester mode is switched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.