System for simplifying the programmable memory to logic interface in FPGA
US6748577B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Jun 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.