Method for fabricating a thin-membrane stencil mask and method for making a semiconductor device using the same
US6749968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | May 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/20
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A stencil mask (12 or 12′) has both a thin membrane layer (106) and a stress controlled layer (104) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer (106) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer (104) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics (30) onto resist (44) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.