Integrated circuit with vertical transistors

US6750095B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Emmerich Bertagnoll · Wien, AT
• Franz Hofmann · Munich, DE
• Bernd Goebel · Dresden, DE
• Wolfgang Roesner · Austin, US

Key dates

• Filing date: May 29, 2001
• Grant date: Jun 15, 2004
• Expiry date: May 29, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/40

Abstract

A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.