Damascene capacitors for integrated circuits

US6750495B1 · kind B1 · utility

Assignee

• Agere Systems Inc. · US

Inventors

• Glenn B. Alers · Santa Cruz, US
• Tseng-Chung Lee · New York, US
• Helen L. Maynard · North Reading, US
• Daniel J. Vitkavage · Winter Garden, US

Key dates

• Filing date: May 12, 1999
• Grant date: Jun 15, 2004
• Expiry date: May 12, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on…