Super-self-aligned trench-gated DMOS with reduced on-resistance
US6750507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2002 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | May 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.