DRAM cell configuration and method for fabricating the DRAM cell configuration

US6750509B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Herbert Benzinger · Birkenfeld, DE
• Frank Richter · Frankfurt, DE

Key dates

• Filing date: May 28, 2002
• Grant date: Jun 15, 2004
• Expiry date: May 28, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0385

Abstract

A DRAM cell configuration is described in which a memory cell in each case has a storage capacitor and a read-out transistor. For connecting to the read-out transistor, a buried strap contact is produced by outdiffusion of dopants from the electrode of the storage capacitor. The buried strap contact is superposed by the implantations of the source/drain region of the read-out transistor, so that the implantations of the source/drain region form the boundary of the space charge zone of a p/n junction of the memory cell.