Two-bit semiconductor memory with enhanced carrier trapping
US6750520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2002 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Mar 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.