Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
US6750675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2002 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Aug 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0094
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.