Method of integrated circuit design checking using progressive individual network analysis
US6751744B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.